`timescale 1ns/1ns

//`define FPGA
module rt7_tcon(
dclk,
rclk,
reset_n,

in_de,
in_r, 
in_g,
in_b, 

chrb,
di, 

in_hact,               
in_end_frame,
in_goa_endframe,
in_data_rst_r,
in_data_rst_f,

pix_sft_en,
sft_dir,
sft_sel,
frvs,
brvs,
chfb,

in_bgi_rst_r,
in_bgi_rst_f,
in_vb_gray,
in_bgi_width_en,
in_bgi_width,

in_sram0_lb1_dout,
in_sram0_lb2_dout,
in_sram1_lb1_dout,
in_sram1_lb2_dout,

out_sram0_lb1_wr,
out_sram1_lb1_wr,
out_sram0_lb2_wr,
out_sram1_lb2_wr,

out_sram0_lb1_rd,
out_sram1_lb1_rd,
out_sram0_lb2_rd,
out_sram1_lb2_rd,

out_sram0_lb1_addr,
out_sram1_lb1_addr,
out_sram0_lb2_addr,
out_sram1_lb2_addr,

out_sram0_lb1_wdata,
out_sram1_lb1_wdata,
out_sram0_lb2_wdata,
out_sram1_lb2_wdata,

out_clk_sel_sram0,
out_clk_sel_sram1,

//out_fpgaf_r,
//out_fpgaf_g,
//out_fpgaf_b,
//out_fpgab_r,
//out_fpgab_g,
//out_fpgab_b,

out_mini_rst,
out_fpr,
out_fpg,
out_fpb,
out_bpr,
out_bpg,
out_bpb

);

input        dclk;
input        rclk;
input        reset_n;

input        in_de;
input [7:0]  in_r; 
input [7:0]  in_g;
input [7:0]  in_b;

input        chrb;
input        di; 

input [10:0] in_hact;                           
input        in_end_frame;
input        in_goa_endframe;
input        in_data_rst_r;
input        in_data_rst_f;   

input        pix_sft_en; 
input        sft_dir;
input [2:0]  sft_sel;
input        frvs;
input        brvs;
input        chfb;

input        in_bgi_rst_r;
input        in_bgi_rst_f;
input [7:0]  in_vb_gray;
input        in_bgi_width_en;
input [10:0] in_bgi_width;

input [23:0] in_sram0_lb1_dout;
input [23:0] in_sram0_lb2_dout;
input [23:0] in_sram1_lb1_dout;
input [23:0] in_sram1_lb2_dout;
             
output out_sram0_lb1_wr;
output out_sram1_lb1_wr;
output out_sram0_lb2_wr;
output out_sram1_lb2_wr;

output out_sram0_lb1_rd;
output out_sram1_lb1_rd;
output out_sram0_lb2_rd;
output out_sram1_lb2_rd;

output [9:0] out_sram0_lb1_addr;
output [9:0] out_sram1_lb1_addr;
output [9:0] out_sram0_lb2_addr;
output [9:0] out_sram1_lb2_addr;

output [23:0] out_sram0_lb1_wdata;
output [23:0] out_sram1_lb1_wdata;
output [23:0] out_sram0_lb2_wdata;
output [23:0] out_sram1_lb2_wdata;

output        out_clk_sel_sram0;
output        out_clk_sel_sram1;

//output [7:0] out_fpgaf_r;
//output [7:0] out_fpgaf_g;
//output [7:0] out_fpgaf_b;
//output [7:0] out_fpgab_r;
//output [7:0] out_fpgab_g;
//output [7:0] out_fpgab_b;

output       out_mini_rst;
output [7:0] out_fpr;
output [7:0] out_fpg;
output [7:0] out_fpb;
output [7:0] out_bpr;
output [7:0] out_bpg;
output [7:0] out_bpb;

//for simulation check 
wire [7:0]  out_sram0_lb1_wdata_r = out_sram0_lb1_wdata [23:16];
wire [7:0]  out_sram0_lb1_wdata_g = out_sram0_lb1_wdata [15:8];
wire [7:0]  out_sram0_lb1_wdata_b = out_sram0_lb1_wdata [7:0];

wire [7:0]  out_sram0_lb2_wdata_r = out_sram0_lb2_wdata [23:16];
wire [7:0]  out_sram0_lb2_wdata_g = out_sram0_lb2_wdata [15:8];
wire [7:0]  out_sram0_lb2_wdata_b = out_sram0_lb2_wdata [7:0];

wire [7:0]  out_sram1_lb1_wdata_r = out_sram1_lb1_wdata [23:16];
wire [7:0]  out_sram1_lb1_wdata_g = out_sram1_lb1_wdata [15:8];
wire [7:0]  out_sram1_lb1_wdata_b = out_sram1_lb1_wdata [7:0];

wire [7:0]  out_sram1_lb2_wdata_r = out_sram1_lb2_wdata [23:16];
wire [7:0]  out_sram1_lb2_wdata_g = out_sram1_lb2_wdata [15:8];
wire [7:0]  out_sram1_lb2_wdata_b = out_sram1_lb2_wdata [7:0];

// degug mode
//rt72 to lb
//sram0_lb1
wire    [6:0] debug_sync_0;
assign debug_sync_0[0]  = out_sram0_lb1_wdata_r[0];
assign debug_sync_0[1]  = out_sram0_lb1_wdata_r[1];
assign debug_sync_0[2]  = out_sram0_lb1_wdata_r[2];
assign debug_sync_0[3]  = out_sram0_lb1_wdata_r[3];
assign debug_sync_0[4]  = out_sram0_lb1_wdata_r[4];
assign debug_sync_0[5]  = out_sram0_lb1_wdata_r[5];
assign debug_sync_0[6]  = out_sram0_lb1_wdata_r[6];

wire    [6:0] debug_sync_1;
assign debug_sync_1[0]  = out_sram0_lb1_wdata_g[0];
assign debug_sync_1[1]  = out_sram0_lb1_wdata_g[1];
assign debug_sync_1[2]  = out_sram0_lb1_wdata_g[2];
assign debug_sync_1[3]  = out_sram0_lb1_wdata_g[3];
assign debug_sync_1[4]  = out_sram0_lb1_wdata_g[4];
assign debug_sync_1[5]  = out_sram0_lb1_wdata_g[5];
assign debug_sync_1[6]  = out_sram0_lb1_wdata_g[6];

wire    [6:0] debug_sync_2;
assign debug_sync_2[0]  = out_sram0_lb1_wdata_b[0];
assign debug_sync_2[1]  = out_sram0_lb1_wdata_b[1];
assign debug_sync_2[2]  = out_sram0_lb1_wdata_b[2];
assign debug_sync_2[3]  = out_sram0_lb1_wdata_b[3];
assign debug_sync_2[4]  = out_sram0_lb1_wdata_b[4];
assign debug_sync_2[5]  = out_sram0_lb1_wdata_b[5];
assign debug_sync_2[6]  = out_sram0_lb1_wdata_b[6];

//sram0_lb2
wire    [6:0] debug_sync_3;
assign debug_sync_3[0]  = out_sram0_lb2_wdata_r[0];
assign debug_sync_3[1]  = out_sram0_lb2_wdata_r[1];
assign debug_sync_3[2]  = out_sram0_lb2_wdata_r[2];
assign debug_sync_3[3]  = out_sram0_lb2_wdata_r[3];
assign debug_sync_3[4]  = out_sram0_lb2_wdata_r[4];
assign debug_sync_3[5]  = out_sram0_lb2_wdata_r[5];
assign debug_sync_3[6]  = out_sram0_lb2_wdata_r[6];

wire    [6:0] debug_sync_4;
assign debug_sync_4[0]  = out_sram0_lb2_wdata_g[0];
assign debug_sync_4[1]  = out_sram0_lb2_wdata_g[1];
assign debug_sync_4[2]  = out_sram0_lb2_wdata_g[2];
assign debug_sync_4[3]  = out_sram0_lb2_wdata_g[3];
assign debug_sync_4[4]  = out_sram0_lb2_wdata_g[4];
assign debug_sync_4[5]  = out_sram0_lb2_wdata_g[5];
assign debug_sync_4[6]  = out_sram0_lb2_wdata_g[6];

wire    [6:0] debug_sync_5;
assign debug_sync_5[0]  = out_sram0_lb2_wdata_b[0];
assign debug_sync_5[1]  = out_sram0_lb2_wdata_b[1];
assign debug_sync_5[2]  = out_sram0_lb2_wdata_b[2];
assign debug_sync_5[3]  = out_sram0_lb2_wdata_b[3];
assign debug_sync_5[4]  = out_sram0_lb2_wdata_b[4];
assign debug_sync_5[5]  = out_sram0_lb2_wdata_b[5];
assign debug_sync_5[6]  = out_sram0_lb2_wdata_b[6];

//sram1_lb1
wire    [6:0] debug_sync_6;
assign debug_sync_6[0]  = out_sram1_lb1_wdata_r[0];
assign debug_sync_6[1]  = out_sram1_lb1_wdata_r[1];
assign debug_sync_6[2]  = out_sram1_lb1_wdata_r[2];
assign debug_sync_6[3]  = out_sram1_lb1_wdata_r[3];
assign debug_sync_6[4]  = out_sram1_lb1_wdata_r[4];
assign debug_sync_6[5]  = out_sram1_lb1_wdata_r[5];
assign debug_sync_6[6]  = out_sram1_lb1_wdata_r[6];

wire    [6:0] debug_sync_7;
assign debug_sync_7[0]  = out_sram1_lb1_wdata_g[0];
assign debug_sync_7[1]  = out_sram1_lb1_wdata_g[1];
assign debug_sync_7[2]  = out_sram1_lb1_wdata_g[2];
assign debug_sync_7[3]  = out_sram1_lb1_wdata_g[3];
assign debug_sync_7[4]  = out_sram1_lb1_wdata_g[4];
assign debug_sync_7[5]  = out_sram1_lb1_wdata_g[5];
assign debug_sync_7[6]  = out_sram1_lb1_wdata_g[6];

wire    [6:0] debug_sync_8;
assign debug_sync_8[0]  = out_sram1_lb1_wdata_b[0];
assign debug_sync_8[1]  = out_sram1_lb1_wdata_b[1];
assign debug_sync_8[2]  = out_sram1_lb1_wdata_b[2];
assign debug_sync_8[3]  = out_sram1_lb1_wdata_b[3];
assign debug_sync_8[4]  = out_sram1_lb1_wdata_b[4];
assign debug_sync_8[5]  = out_sram1_lb1_wdata_b[5];
assign debug_sync_8[6]  = out_sram1_lb1_wdata_b[6];

//sram1_lb2
wire    [6:0] debug_sync_9;
assign debug_sync_9[0]  = out_sram1_lb2_wdata_r[0];
assign debug_sync_9[1]  = out_sram1_lb2_wdata_r[1];
assign debug_sync_9[2]  = out_sram1_lb2_wdata_r[2];
assign debug_sync_9[3]  = out_sram1_lb2_wdata_r[3];
assign debug_sync_9[4]  = out_sram1_lb2_wdata_r[4];
assign debug_sync_9[5]  = out_sram1_lb2_wdata_r[5];
assign debug_sync_9[6]  = out_sram1_lb2_wdata_r[6];

wire    [6:0] debug_sync_10;
assign debug_sync_10[0]  = out_sram1_lb2_wdata_g[0];
assign debug_sync_10[1]  = out_sram1_lb2_wdata_g[1];
assign debug_sync_10[2]  = out_sram1_lb2_wdata_g[2];
assign debug_sync_10[3]  = out_sram1_lb2_wdata_g[3];
assign debug_sync_10[4]  = out_sram1_lb2_wdata_g[4];
assign debug_sync_10[5]  = out_sram1_lb2_wdata_g[5];
assign debug_sync_10[6]  = out_sram1_lb2_wdata_g[6];

wire    [6:0] debug_sync_11;
assign debug_sync_11[0]  = out_sram1_lb2_wdata_b[0];
assign debug_sync_11[1]  = out_sram1_lb2_wdata_b[1];
assign debug_sync_11[2]  = out_sram1_lb2_wdata_b[2];
assign debug_sync_11[3]  = out_sram1_lb2_wdata_b[3];
assign debug_sync_11[4]  = out_sram1_lb2_wdata_b[4];
assign debug_sync_11[5]  = out_sram1_lb2_wdata_b[5];
assign debug_sync_11[6]  = out_sram1_lb2_wdata_b[6];




//connect wire (module to module)
// rt70 to rt71
wire        nml_de;
wire [23:0] nml_rgb;
wire        data_sft_rgb;

// rt71 to rt72
wire out_xdio_rt72;
wire out_sram0_lb1_wr;
wire out_sram1_lb1_wr;
wire out_sram0_lb2_wr;
wire out_sram1_lb2_wr;

wire out_sram0_lb1_rd;
wire out_sram1_lb1_rd;
wire out_sram0_lb2_rd;
wire out_sram1_lb2_rd;


rt70_subpixel_ctrl U_rt70_subpixel_ctrl(
.dclk                  (dclk             ),
.reset_n               (reset_n          ),

.in_de                 (in_de            ),
.in_r                  (in_r             ),
.in_g                  (in_g             ),
.in_b                  (in_b             ),
.in_end_frame          (in_end_frame     ),
.in_goa_endframe       (in_goa_endframe  ),

.pix_sft_en            (pix_sft_en       ),
.sft_dir               (sft_dir          ),
.sft_sel               (sft_sel          ),

.chrb                  (chrb             ),
.di                    (di               ),

.nml_de                (nml_de           ),
.nml_rgb               (nml_rgb          ),
.data_sft_rgb          (data_sft_rgb     )

);



rt71_line_buffer_ctrl U_rt71_line_buffer_ctrl(
.dclk                    (dclk                ),
.rclk                    (rclk                ),
.reset_n                 (reset_n             ),
                                            
.res                     (in_hact             ),          
.in_end_frame            (in_end_frame        ),
.in_goa_endframe         (in_goa_endframe     ),
.in_data_rst_r           (in_data_rst_r       ),                 
.in_data_rst_f           (in_data_rst_f       ),           

.pix_sft_en              (pix_sft_en          ),
.sft_dir                 (sft_dir             ),
.sft_sel                 (sft_sel             ),
.data_sft_rgb            (data_sft_rgb        ),
.frvs                    (frvs                ),
.brvs                    (brvs                ),

.in_nml_de               (nml_de              ),
.in_nml_rgb              (nml_rgb             ),

.out_xdio_rt72           (out_xdio_rt72       ),
.out_sram0_lb1_wr        (out_sram0_lb1_wr    ),
.out_sram1_lb1_wr        (out_sram1_lb1_wr    ),   
.out_sram0_lb2_wr        (out_sram0_lb2_wr    ),
.out_sram1_lb2_wr        (out_sram1_lb2_wr    ),
                         
.out_sram0_lb1_rd        (out_sram0_lb1_rd    ),
.out_sram1_lb1_rd        (out_sram1_lb1_rd    ),
.out_sram0_lb2_rd        (out_sram0_lb2_rd    ),
.out_sram1_lb2_rd        (out_sram1_lb2_rd    ),
                         
.out_sram0_lb1_addr      (out_sram0_lb1_addr  ),
.out_sram1_lb1_addr      (out_sram1_lb1_addr  ),
.out_sram0_lb2_addr      (out_sram0_lb2_addr  ),
.out_sram1_lb2_addr      (out_sram1_lb2_addr  ),
                         
.out_sram0_lb1_wdata     (out_sram0_lb1_wdata ),
.out_sram1_lb1_wdata     (out_sram1_lb1_wdata ),
.out_sram0_lb2_wdata     (out_sram0_lb2_wdata ),
.out_sram1_lb2_wdata     (out_sram1_lb2_wdata ),

.out_clk_sel_sram0       (out_clk_sel_sram0   ),
.out_clk_sel_sram1       (out_clk_sel_sram1   )

);

rt72_mini_lvds_macro U_rt72_mini_lvds_macro(
 .dclk                   (dclk             ),
 .rclk                   (rclk             ),
 .reset_n                (reset_n          ),
 .in_end_frame           (in_end_frame     ),
 .in_goa_endframe        (in_goa_endframe  ),
 .in_xdio                (out_xdio_rt72    ),
 .chfb                   (chfb             ),

 .in_bgi_rst_r            (in_bgi_rst_r    ),
 .in_bgi_rst_f            (in_bgi_rst_f    ),
 .in_vb_gray              (in_vb_gray      ),
 .in_bgi_width_en         (in_bgi_width_en ),
 .in_bgi_width            (in_bgi_width    ),
 
 .in_sram0_lb1_wen       (out_sram0_lb1_wr ),
 .in_sram0_lb2_wen       (out_sram0_lb2_wr ),
 .in_sram1_lb1_wen       (out_sram1_lb1_wr ),
 .in_sram1_lb2_wen       (out_sram1_lb2_wr ),

 .in_sram0_lb1_cen       (out_sram0_lb1_rd ),
 .in_sram0_lb2_cen       (out_sram0_lb2_rd ),
 .in_sram1_lb1_cen       (out_sram1_lb1_rd ),
 .in_sram1_lb2_cen       (out_sram1_lb2_rd ),

 .in_sram0_lb1_dout      (in_sram0_lb1_dout),
 .in_sram0_lb2_dout      (in_sram0_lb2_dout),
 .in_sram1_lb1_dout      (in_sram1_lb1_dout),
 .in_sram1_lb2_dout      (in_sram1_lb2_dout),
  
//`ifdef FPGA
//  .out_fpgaf_r           (out_fpgaf_r      ),
//  .out_fpgaf_g           (out_fpgaf_g      ),
//  .out_fpgaf_b           (out_fpgaf_b      ),
//  .out_fpgab_r           (out_fpgab_r      ),
//  .out_fpgab_g           (out_fpgab_g      ),
//  .out_fpgab_b           (out_fpgab_b      )
//`else
 .out_mini_rst           (out_mini_rst     ),
 .out_fpr                (out_fpr          ),
 .out_fpg                (out_fpg          ),
 .out_fpb                (out_fpb          ),
 .out_bpr                (out_bpr          ),
 .out_bpg                (out_bpg          ),
 .out_bpb                (out_bpb          )
//`endif


);

endmodule